Redundancy and its implementation has been one of the more significant challenges in memory chips. In many applications, the effects of a redundancy implementation on the die area as well as the access time are important aspects of a memory, especially in larger and more dense memory chips.
In some redundancy approaches, the addresses are received and compared in parallel with selection of the decoders. Typically, if it is determined that the address is a repaired location, then the redundancy circuit is engaged. The redundancy circuit sends a signal to the regular decoder to disengage or deselect the regular array, and then select the redundant element. Detection of a match on the incoming address for a redundant element usually takes approximately 5 to 10 nanoseconds, during which time the decoders start selecting the proper memory elements. On very high density parts, the decoder lines have tens of picofarad capacitive load and thus require very large drivers. As such, the deselect signal is usually not near the last stages of the decoder due to the area consumed by the large number of decoder drivers.
With such large capacitive loads, the last stage requires approximately 5 nanoseconds to select and deselect. After the 5 to 10 nanoseconds of delay for matching detection circuit, the redundancy circuit will send a signal to instruct the regular decoders to deselect. Because the deselection stage is not the last stage of the decoder, it will take additional time for the regular decoder to turn off. If a redundant element is accessed, it will be generally slower than the actual element by approximately 10 to 20 nanoseconds. This accounts for a significant speed loss. With very large density memories, 50% to 80% of the dies that pass have some redundant elements.
Another feature that is used in some redundant schemes is the replacement of the entire byte (or word) if a bit is found to be defective within that word. If eight redundant columns were to be replaceable, one must design 64 columns in the array. On a four-megabit flash circuit, for example, this amounts to approximately five mils more on one dimension of the chip, which translates to many thousands of mils of additional square area.
Accordingly, there is a need for a memory circuit with a redundancy scheme that improves upon die area and access speed.